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INTEGRATED CIRCUITS
DATA SHEET
74ALVCH16623 16-bit transceiver with dual enable; 3-state
Product specification Supersedes data of 1998 Aug 31 File under Integrated Circuits, IC24 1999 Sep 20
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
FEATURES * Complies with JEDEC standard no. 8-1A * CMOS low power consumption * Direct interface with TTL levels * MULTIBYTETM flow-through standard pin-out architecture * All data inputs have bus hold circuitry * Output drive capability 50 transmission lines at 85 C * Current drive 24 mA at 3.0 V. DESCRIPTION
74ALVCH16623
The 74ALVCH16623 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74ALVCH16623 is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. This 16-bit bus transceiver is designed for asynchronous two-way communication between data buses. The control function implementation allows maximum flexibility in timing. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the enable inputs (nOEAB, nOEBA). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual enable function configuration gives this transceiver the capability to store data by simultaneous enabling of nOEAB and nOEBA. Each output reinforces its input in this transceiver configuration. Thus, when all control inputs are enabled and all other data sources to the four sets of the bus lines are at high-impedance OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes appearing on the two double sets of buses will be complementary. This device can be used as two 8-bit transceivers or one 16-bit transceiver. To ensure the high-impedance state during power-on or power-down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
QUICK REFERENCE DATA Ground = 0; Tamb = 25 C; tr = tf = 2.5 ns. SYMBOL tPHL/tPLH CI/O CI CPD PARAMETER propagation delay nAn, nBn to nBn, nAn input/output capacitance input capacitance power dissipation capacitance per buffer notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in Volts; (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC. 1999 Sep 20 2 35 5 pF pF CONDITIONS CL = 30 pF; VCC = 2.5 V CL = 50 pF; VCC = 3.3 V TYPICAL 2.0 1.9 10.0 3.0 ns ns pF pF UNIT
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74ALVCH16623DGG FUNCTION TABLE See note 1. INPUTS nOEAB L H L H Note 1. H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. PINNING PIN 1, 24 2, 3, 5, 6, 8, 9, 11, 12 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 13, 14, 16, 17, 19, 20, 22, 23 25, 48 26, 27, 29, 30, 32, 33, 35, 36 37, 38, 40, 41, 43, 44, 46, 47 SYMBOL 1OEAB, 2OEAB 1B0 to 1B7 GND VCC 2B0 to 2B7 2OEBA, 1OEBA 2A7 to 2A0 1A7 to 1A0 nOEBA L H H L nAn A=B inputs Z A=B -40 to +85 C PINS 48 PACKAGE TSSOP
74ALVCH16623
MATERIAL plastic
CODE SOT362-1
INPUTS/OUTPUTS nBn inputs B=A Z B=A
DESCRIPTION output enable input (active HIGH) data inputs/outputs ground (0 V) DC supply voltage data inputs/outputs output enable input (active LOW) data inputs/outputs data inputs/outputs
1999 Sep 20
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Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
fpage
1OEAB 1B0 1B1 GND 1B2 1B3 VCC 1B4 1B5
1 2 3 4 5 6 7 8 9
48 1OEBA 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 1A4 40 1A5 39 GND 38 1A6 44 1A2 1B2 43 1A3 1B3 41 1A4 1B4 40 1A5 1B5 38 1A6 1B6 37 1A7 1B7 12 11 26 2A7 2B7 23 9 27 2A6 2B6 22 8 29 2A5 2B5 20 6 30 2A4 2B4 19 5 32 2A3 2B3 17 46 1A1 1B1 3 33 2A2 2B2 16 47 1A0 1B0 2 35 2A1 2B1 14 36 2A0 2B0 13 1 1OEAB 24 2OEAB 48 1OEBA 25 2OEBA
GND 10 1B6 11 1B7 12 2B0 13 2B1 14 GND 15 2B2 16 2B3 17 VCC 18 2B4 19 2B5 20 GND 21 2B6 22 2B7 23 2OEAB 24
MNA307
16623
37 1A7 36 2A0 35 2A1 34 GND 33 2A2 32 2A3 31 VCC 30 2A4 29 2A5 28 GND 27 2A6 26 2A7 25 2OEBA
MNA308
Fig.1 Pin configuration.
Fig.2 Logic symbol.
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Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
48 handbook, halfpage 1
1EN1 1EN2
25 24
2EN1 2EN2
1 47 46 44 43 41 40 38 37 2 2 3 5 6 8 9 11 12 36 35 33 32 30 29 27 26
1 2 13 14 16 17 19
MNA310
handbook, halfpage
VCC
data input
to internal circuit
20 22 23
MNA309
Fig.3 IEC logic symbol.
Fig.4 Bus hold circuit.
1999 Sep 20
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Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER DC supply voltage for max. speed performance for max. speed performance for low-voltage applications VI VO Tamb tr, ft DC input voltage DC output voltage operating ambient temperature input rise and fall times in free air VCC = 2.3 to 3.0 V VCC = 3.0 to 3.6 V LIMITING VALUES CL = 30 pF CL = 50 pF 2.3 3.0 1.2 0 0 -40 0 0 CONDITIONS MIN.
74ALVCH16623
TYP. 2.5 3.3 2.4 - - - - -
MAX. 2.7 3.6 3.6 VCC VCC +85 20 10
UNIT V V V V V C ns/V ns/V
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 55 C the value of Ptot derates linearly with 8 mW/K. PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or GND current storage temperature power dissipation VI < 0 note 1 VO > VCC or VO < 0 note 1 VO = 0 to VCC CONDITIONS MIN. -0.5 - -0.5 - -0.5 - - -65 for temperature range: -40 to +125 C; - note 2 MAX. +4.6 -50 +4.6 50 VCC + 0.5 50 100 +150 600 UNIT V mA V mA V mA mA C mW
1999 Sep 20
6
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
DC CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL VIH VIL VOH PARAMETER VI (V) HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VIH or VIL IO = -100 A IO = -6 mA IO = -12 mA IO = -12 mA IO = -12 mA IO = -24 mA VOL LOW-level output voltage VIH or VIL IO = 100 A IO = 6 mA IO = 12 mA IO = 12 mA IO = 24 mA Il IOZ ICC ICC input leakage current 3-state output OFF-state current quiescent supply voltage VCC or GND VIH or VIL VCC or GND VO = VCC or GND IO = 0 IO = 0 OTHER VCC (V) 2.3 to 2.7 1.7 2.7 to 3.6 2.0 2.3 to 2.7 - 2.7 to 3.6 - 2.3 2.3 2.7 3.0 3.0 2.3 2.3 2.7 3.0
74ALVCH16623
Tamb = -40 TO +85 C MIN. TYP.(1) 1.2 1.5 1.2 1.5 MAX. - - 0.7 0.8 - - - - - - 0.20 0.40 0.70 0.40 0.55 5 10 40 750
UNIT V V V
2.3 to 3.6 VCC - 0.2 VCC VCC - 0.3 VCC - 0.08 VCC - 0.6 VCC - 0.26 VCC - 0.5 VCC - 0.14 VCC - 0.6 VCC - 0.09 VCC - 1.0 VCC - 0.28 GND 0.07 0.15 0.14 0.27 0.1 0.1 0.2 150 - - - -
2.3 to 3.6 -
V
2.3 to 3.6 - 2.3 to 3.6 - 2.3 to 3.6 - 2.3 to 3.6 -
A A A A
additional quiescent supply VCC - 0.6 current given per data I/O pin with bus hold bus hold LOW sustaining current bus hold HIGH sustaining current bus hold LOW overdrive current bus hold LOW overdrive current 0.7(2) 0.8(2) 1.7(2) 2.0(2)
IBHL IBHH IBHLO IBHHO Notes
2.3(2) 3.0(2) 2.3(2) 3.0(2) 3.6(2) 3.6(2)
45 75 -45 -75 500 -500
- 150 -175 - -
- - - - - -
A A A A
1. All typical values are measured at Tamb = 25 C. 2. Valid for data inputs of bus hold parts.
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Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
AC CHARACTERISTICS FOR VCC = 2.3 TO 2.7 V Ground = 0 V; tr = tf 2.0 ns; CL = 30 pF. TEST CONDITIONS SYMBOL tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPZH/tPZL tPHZ/tPLZ Note 1. All typical values are measured at Tamb = 25 C and VCC = 2.5 V. AC CHARACTERISTICS FOR VCC = 2.7 V AND VCC = 3.0 TO 3.6 V Ground = 0 V; tr = tf 2.5 ns; CL = 50 pF. TEST CONDITIONS SYMBOL tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPZH/tPZL tPHZ/tPLZ PARAMETER WAVEFORMS propagation delay nAn, nBn to nBn, nAn 3-state output enable time nOEAB to nBn 3-state output disable time nOEBA to nAn 3-state output enable time nOEAB to nBn 3-state output disable time nOEBA to nAn see Figs 5 and 8 see Figs 7 and 8 see Figs 6 and 8 see Figs 7 and 8 see Figs 6 and 8 VCC (V) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 PARAMETER WAVEFORMS propagation delay nAn, nBn to nBn, nAn 3-state output enable time nOEAB to nBn 3-state output disable time nOEBA to nAn 3-state output enable time nOEAB to nBn 3-state output disable time nOEBA to nAn see Figs 5 and 8 see Figs 7 and 8 see Figs 6 and 8 see Figs 7 and 8 see Figs 6 and 8 VCC (V)
74ALVCH16623
Tamb = -40 TO +85 C MIN. TYP.(1) 2.4 3.0 3.0 2.8 2.4 MAX. 3.5 5.0 5.1 4.5 4.0
UNIT ns ns ns ns ns
2.3 to 2.7 1.0 2.3 to 2.7 2.3 to 2.7 2.3 to 2.7 2.3 to 2.7 1.0 1.0 1.0 1.0
Tamb = -40 TO +85 C MIN. TYP.(1) 2.5 2.6(2) 2.8 2.6(2) 3.3 2.8(2) 3.8 3.3(2) 3.2 3.0(2) MAX. 3.4 3.1 4.5 4.0 5.0 4.2 5.4 4.6 4.5 4.3
UNIT ns ns ns ns ns
Notes 1. All typical values are measured at Tamb = 25 C. 2. Typical values at VCC = 3.3 V.
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Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
AC WAVEFORMS Notes: VCC = 2.3 to 2.7 V VM = 0.5VCC; VX = VOL + 150 mV; VY = VOH - 150 mV; VI = VCC;
74ALVCH16623
handbook, halfpage VI
VOL and VOH are typical output voltage drop that occur with the output load.
VM
nAn, nBn input GND tPHL VOH nBn, nAn output VOL
Notes: VCC = 3.0 to 3.6 V and VCC = 2.7 V VM = 1.5 V;
tPLH
VX = VOL + 300 mV; VY = VOH - 300 mV; VI = 2.7 V;
VM
MNA311
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5
The input nAn, nBn to output nBn, nAn propagation delay times.
handbook, full pagewidth
VI nOEBA input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM tPZL VM
VM VX tPZH
outputs disabled
outputs enabled
MNA312
Fig.6 3-state enable and disable times for nOEBA input.
1999 Sep 20
9
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
handbook, full pagewidth
VI nOEAB input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM
outputs disabled
outputs enabled
MNA313
Fig.7 3-state enable and disable times for nOEAB times.
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 500 VO
RL 500
2 x VCC open GND
MNA296
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 open 2 x VCC GND VCC <2.7 V VCC VI
2.7 to 3.6 V 2.7 V
Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter "AC characteristics"). RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
1999 Sep 20
10
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
PACKAGE OUTLINE TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
74ALVCH16623
SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153ED EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-02-03 95-02-10
1999 Sep 20
11
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
74ALVCH16623
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Sep 20
12
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
Suitability of surface mount IC packages for wave and reflow soldering methods
74ALVCH16623
SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not REFLOW(1)
1999 Sep 20
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Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
NOTES
74ALVCH16623
1999 Sep 20
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Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
NOTES
74ALVCH16623
1999 Sep 20
15
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245004/02/pp16
Date of release: 1999
Sep 20
Document order number:
9397 750 05254

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